Electrical Circuit Design Principles

What are the reasons why transformers are sometimes grounded through resistance, reactance, or capacitance? How are ground source connections made? Becoming a ground source is more complicated than just connecting a transformer connection point, normally the neutral, to the ground. It has to facilitate the ability for ground current to be pulled up at one spot in the grid (the ground source) and put back down in the ground, normally at a ground fault. A ground source is a delta-wye or zig-zag type transformer, as they are the only ones that can pull ground current from the earth. A wye-grounded-wye-grounded transformer is connected to the earth but does not facilitate pulling ground current out of the ground since the ground current flowing into one wye goes into the ground and up the ground connection into the other wye. Ground current passes through it, and it is not a source, even though its neutrals are connected to the ground. Being able to pull ground current out of the earth is what makes something a ground source, and zig-zag and delta-wye-grounded connections can do this. What are the reasons for placing an impedance in a ground source connection? Since this impedance hinders the flow of ground current during an imbalance, like a ground fault, it limits the available fault current for ground faults. This can be beneficial to reduce the damage to equipment like cables, transformers, and generator windings, and potentially reduce available arc flash energies. Additionally, a perk versus ungrounded systems is that the voltages are more stable and don’t see a 173% voltage increase on the healthy phases during an SLG fault, or higher, due to intermittent arcing. What are the types of impedances used to ground? Resistive grounding is the most common impedance used to ground a source through an impedance. It reduces the available ground current and helps mitigate voltage issues. Reactance grounding can reduce fault currents, though usually to a lesser degree than resistive grounding, and help provide stable voltages. The reactance can offset the ground capacitance of long transmission lines and reduce the severity of arcing faults, which with something like a Peterson Coil, can be reduced to the point that the arc extinguishes. Additionally, since the impedance is reactive rather than resistive, not as much energy is wasted as heat during slight imbalances or ground faults. Capacitive grounding is not common, as the energy stored in the capacitance can cause voltage spikes and resonance issues. Transformers are sometimes, very rarely, grounded through capacitance to block quasi-DC currents that are induced in the ground during solar storms. These quasi-DC currents flow between different ground points with different earth potentials, and since they are DC, they can saturate the transformer and damage it. The ground capacitor blocks these quasi-DC ground loops. #utilities #electricalengineering #renewables #energystorage

Why Most SiC #Inverter Failures Are Layout Failures Forget blaming the #SiC die or the gate driver. At hundreds of volts and hundreds of amps, the thing that actually breaks is almost always copper and geometry, not silicon. At 800 V and multi-hundred-kW power levels, parasitics stop being “second order.” A few nanohenries of DC-link loop inductance will ring with device capacitances and kick V_DS into catastrophic overshoot at turn-off. We’ve repeatedly seen systems spike well beyond the rail simply because the caps and busbars weren’t essentially welded to the half-bridge. Key failure mechanisms I keep seeing in the lab and field: • DC-link loop inductance → huge overshoot. Any length in the high-current loop stores energy that gets dumped into the MOSFET at turn-off. Tighten that loop first. • Gate ↔ power loop coupling → false turn-on. Fast dv/dt pumps current through Miller capacitances. If the gate loop is loose, you get brief gate-source glitches that are enough to trigger shoot-through on SiC. • Uneven current sharing and resonances. Paralleled devices double di/dt but any trace-length mismatch produces a device that hogs the surge. Common-source inductance feeds back into timing and creates deterministic imbalance. • “Random” failures aren’t random. Simulators often under-represent parasitic loops. What looks safe on paper rings differently once copper, assembly tolerances, and temperature swing appear. Teams often react by tweaking gate resistances or adding snubbers. Those are band-aids. The real fix is architectural: design the switching cell and the power loop first, then pick devices. Practical design priorities that actually stop crashes: • Minimize DC-link loop L with laminated/balanced busbars • Place low-ESR bulk and HF caps millimetres from the half-bridge • Make gate loops ultra-compact and electrically isolated from power loops • Keep parallel device source inductance matched and symmetric SiC enables extreme switching, but it also exposes every #PCBLayout failing. If your inverter explodes on first power, don’t start by blaming the MOSFET. Rework the copper. Reliable SiC inverters start with power-loop architecture and layout, not the transistor. Image credit: EEWorld. The inverter shown is the #Hyundai IONIQ 5 800 V traction inverter, used here as a representative example of modern high-power SiC inverter layout. #PowerElectronics #InverterDesign #ReliabilityEngineering #ElectricVehicles #HighPowerDensity #MotorDrives

Me today dealing with some EMC issues… 🧙♂️🪄🐉 EMC might feel like black magic sometimes, but it’s not all spells and wand-waving. Here’s the checklist I worked through today to troubleshoot: 1️⃣ 𝗕𝗲 𝘄𝗮𝗿𝘆 𝗼𝗳 𝘄𝗶𝗿𝗶𝗻𝗴 𝗮𝗰𝘁𝗶𝗻𝗴 𝗹𝗶𝗸𝗲 𝗮𝗻 𝗮𝗻𝘁𝗲𝗻𝗻𝗮. Anything with wiring can pick up noise and radiate it—even cables that seem unrelated to your core system. If the cable isn’t critical, remove it and retest to isolate the problem. If you can’t remove it, try adding a ferrite ring to the cable as close to the board as possible On the PCB, ferrite beads or chokes can also help suppress noise if you’ve got space to add them. 2️⃣ 𝗦𝗹𝗼𝘄 𝗱𝗼𝘄𝗻 𝘆𝗼𝘂𝗿 𝗠𝗢𝗦𝗙𝗘𝗧 𝗴𝗮𝘁𝗲 𝗱𝗿𝗶𝘃𝗲 𝘀𝗶𝗴𝗻𝗮𝗹𝘀. This is one of the top culprits for EMI on motor drive boards. Increasing both the turn-on and turn-off resistors for your MOSFET gate drive slows the rise and fall times of the signal, which directly cuts down on emissions. 3️⃣ 𝗥𝗲𝗱𝘂𝗰𝗲 𝗣𝗪𝗠 𝗳𝗿𝗲𝗾𝘂𝗲𝗻𝗰𝗶𝗲𝘀. We had a 250kHz PWM signal driving a battery charger boost converter. The lab results weren’t happy, so we made some changes: - Dropped the frequency to 75kHz. - Increased the inductor value to match the new frequency. - Slowed down the MOSFET rise time (see point 2). This got us under the threshold—barely (around 2dB). We’ll reduce the charge current by about 15% to get a little more breathing room. 4️⃣ 𝗖𝗵𝗲𝗰𝗸 𝘆𝗼𝘂𝗿 𝗿𝗲𝘁𝘂𝗿𝗻 𝗽𝗮𝘁𝗵𝘀. High-current or high-frequency signals need clean return paths—no exceptions. In our case, we were stuck with a 2-layer PCB (budget constraints, of course), and the ground return path for the low-side MOSFET gate drive signal ended up being pretty big. I spotted a way to reduce the loop area by adding a via. We drilled a quick hole in the board and connected it with a wire. Not pretty, but it worked! The layout will need redoing, but this hack let us verify the solution at the test lab. If you haven’t already, check out 𝗔 𝗛𝗮𝗻𝗱𝗯𝗼𝗼𝗸 𝗼𝗳 𝗕𝗹𝗮𝗰𝗸 𝗠𝗮𝗴𝗶𝗰 𝗯𝘆 𝗛𝗼𝘄𝗮𝗿𝗱 𝗝𝗼𝗵𝗻𝘀𝗼𝗻. It’s the go-to resource for high speed digital electronics theory, and will let you analyse EMC issues way more effectively. What are your favorite resources for EMC troubleshooting? Drop them below—I’m always on the lookout for more tools/knowledge to add to my wizarding arsenal! 🪄 ------------- 🔔 Follow Ryan Dunwoody for more hardware chat 🚀 ♻️ Repost if you're an EMC wizard (or would like to be) 🧙♂️

A client contacted me to troubleshoot a battery-powered device that stopped working shortly after a full charge. The system used a 3.7 V Li-ion battery, and as soon as I looked at the schematic, something was clearly wrong. They used: A Schottky diode (0.55 V drop) for reverse-polarity protection A 3.3 V LDO regulator powered directly from the battery That combination instantly limits the usable voltage range. After the diode drop, the LDO can only regulate while the battery is above ~3.9 V. Once it falls near 3.8 V, the output collapses, and the system shuts down. I replaced the diode with a P-channel MOSFET for low-loss reverse protection, and swapped the LDO for a buck-boost converter that keeps 3.3 V stable across the full 3.0–4.2 V battery range. Simple changes, but the device started working perfectly. #IoT #BuckBoost #LDO #ReverseProtection #Hardware

🔍 Understanding Buck vs. Boost Converters (Simulation): The main difference: ↗️ Boost Converter (Step-Up) Elevates voltage to meet the needs of higher-voltage loads such as LED arrays, motor drivers, or sensor systems (e.g., 12V to 24V). Both converter types are fundamental to power management in embedded systems, renewable energy, automotive applications, and industrial automation. ↘️ Buck Converter (Step-Down) Efficiently steps down voltage to power lower-voltage components such as microcontrollers, logic circuits, or communication modules (e.g., 12V to 5V). ⚙️ Design Factors You Shouldn’t Ignore: When working with buck or boost converters, it’s not just about input and output voltage. A few behind-the-scenes factors can make a big difference: 🔁 Duty Cycle Consider this as the switch's "on/off cycle". In a buck converter, you’ll typically see shorter on-times (lower duty cycle) because you’re reducing voltage. 📡 Switching Frequency This is how fast the converter turns the switch on and off. Higher frequencies can shrink your inductors and capacitors (great for saving board space). But they can also increase switching losses, so there's a trade-off between size and efficiency. ⚡ Load Behavior Your converter doesn’t operate in a vacuum; it responds to the load. Sudden changes in current draw (like turning a motor on) can affect stability. The converter’s ability to respond quickly and stay stable depends on how well it’s tuned to the expected load profile. #PowerElectronics #Engineering #HardwareDesign #DCConverters #BuckBoost #ElectronicsDesign

🔴 MediaTek presents the blueprint for next-gen data center scaling in #IEEE. The paper "Heterogeneous Integration in Co-Packaged Optics" proves that mastering multi-physics interactions, will define the next decade of #CPO #HeterogeneousIntegration. While the industry races to support the explosive bandwidth demands of Generative AI and LLMs, placing hot XPUs, HBMs, and optical transceivers tightly together on a single substrate creates severe electrical, optical, and thermal bottlenecks. MediaTek takes a comprehensive look at these heterogeneous integration (HI) challenges and outlines the advanced mitigation strategies required to make commercial CPO a reality. 1️⃣ The Heat Barrier: #ThermalCrosstalk & #TIMs High-power main dies create a harsh thermal environment that threatens the reliability of adjacent HBMs and temperature-sensitive photonic circuits, where even slight temperature changes alter the refractive index and destabilize the lasers. Overcoming this requires moving beyond standard cooling to advanced liquid-based microchannels and ultra-thin Thermal Interface Materials (TIMs), utilizing metal or carbon-based solutions like diamond with thermal conductivities well over 100 W/mK. 2️⃣ Taming 224Gbps SerDes: #SIPI & #LossyChannels When pushing narrow-and-fast SerDes protocols beyond 100 Gbps, the required Nyquist frequency can exceed 80 GHz, causing package insertion loss to skyrocket. To maintain Signal and Power Integrity (SIPI), the industry must adopt lower-loss dielectric materials and deploy clever layout techniques, such as skip-layer routing and Hex bump patterns, which are crucial for suppressing unexpected cavity resonances. 3️⃣ The Substrate Dilemma: #Glass vs #Silicon Choosing the right interposer material dictates the entire system's limits. While Silicon interposers offer proven, highly reliable, and precise processes, they are electrically lossy and cannot support long-reach, high-frequency SerDes. Glass is rapidly emerging as a powerful alternative, offering tunable CTE for low warpage and excellent low-loss properties that can support high-speed SerDes beyond 200 Gbps. 💡 My Take: MediaTek's roadmap highlights that successful CPO isn't just about putting optics on a board. It's about holistically co-designing the entire multi-physics ecosystem, from the cooling fluids to the glass substrates and skip-layer traces. The transition from organic and silicon interposers to glass might just be the ultimate key to unlocking massive, panel-scale AI compute clusters. What are your thoughts on the readiness of the supply chain to adopt glass interposers for high-volume 3D CPO manufacturing? 👇 Link in the comments #AdvancedPackaging #SiliconPhotonics #HardwareArchitecture #Metrology #3DIC #DataCenter #AIHardware Intel Corporation TSMC Samsung Electronics SK hynix NVIDIA AMD Applied Materials Lam Research ASML Tokyo Electron US Corning Incorporated SCHOTT GlobalFoundries

🔋 In a microgrid, multiple distributed sources must proportionately share the load demand while simultaneously maintaining voltage and, in the case of AC microgrids, also frequency stability. Broadly, the approaches to address this challenge fall into two main categories: those that rely on communication links between the inverter modules and those that operate without communications, typically leveraging the droop concept. 🔌 Communication-based control generally offers excellent voltage regulation and proper power sharing, often without requiring secondary control. They achieve tight current sharing, high power quality, and fast transient response, while also reducing circulating currents. Their primary disadvantages include increased system cost due to the need for communication lines, which can also be susceptible to interference over long distances, thereby reducing system reliability and expandability. ⚡ Droop-based control methods tend to be cost-effective, more reliable, and easier to expand due to their plug-and-play capability, as they do not require communication links. Droop control inherently leads to frequency and voltage deviations and has a slow dynamic response. They can also cause circulating currents due to line impedance mismatches and perform poorly with fluctuating renewable energy sources. The key droop methods are: 1️⃣ Conventional Frequency/Voltage Droop Control: It is easy to implement and offers high expandability, modularity, and flexibility. Its drawbacks include being affected by physical parameters, resulting in poor voltage-frequency regulation, slow dynamic response, and poor harmonic sharing. 2️⃣ Virtual Structure-Based Methods: These are generally not affected by physical parameters and offer improved power-sharing performance and system stability. They can also handle linear/nonlinear loads and mitigate harmonic voltages. However, voltage regulation isn't always guaranteed, and they may require knowledge of physical parameters and low-bandwidth communication. 3️⃣ Construction-and-Compensation-Based Methods: These generally offer improved voltage regulation, system stability, and power sharing. They can reduce reactive power sharing errors and are often robust to communication delays. 4️⃣ Common Variable-Based Control Method: This approach achieves accurate proportional load sharing and is robust to system parameter variations, being unaffected by physical parameters. The main challenge is the difficulty in measuring the common bus voltage over long distances, and a common voltage may not exist in complex or distributed systems. #microgrids #powerelectronics #lvdc #renewables #cleanenergy #control

The death of a 12 V battery-powered circuit is almost always avoidable. And yet, it happens every day. Reverse polarity, automotive transients, aggressive hot-plugging, rushed users making quick connections. Some systems fail instantly. Others degrade slowly until the field returns them to the bench. The classic solution is a series diode: fast and inexpensive. But it introduces a permanent voltage drop, continuous power dissipation, and unnecessary thermal stress at higher currents. Simple, yes. Optimal, rarely. A controller such as the LM5050, driving an external N-MOSFET, changes the equation at a circuit level. Forward conduction occurs through the MOSFET’s low Rds(on), drastically reducing losses compared to a diode. During reverse polarity events, the controller quickly turns the MOSFET off, blocking reverse current instead of relying on a passive junction. The result is a protection stage that behaves efficiently in normal operation and decisively during faults. Combined with a properly placed TVS, a coordinated fuse, and disciplined layout, the input stage becomes a controlled energy interface rather than a fragile entry point. It is not the lowest-cost option in the BOM. But it is often the lowest-cost decision over the product’s lifetime. Designing hardware is often like living in a quantum projection between life and death. #PCB #hardware #kicad

🔋 BandGap Reference – The Omnipresent IC Block In the world of analog and mixed-signal design, one block quietly sits at the heart of nearly every precision circuit — the BandGap Reference (BGR). From voltage regulators to ADCs, PLLs, and sensors — the BGR ensures everything runs on a stable and temperature-independent reference, typically around 1.2 V, derived from the physical bandgap energy of silicon itself. 🧩 Core Concept The BGR elegantly combines two opposing temperature behaviors: CTAT (Complementary To Absolute Temperature) – decreases with temperature. PTAT (Proportional To Absolute Temperature) – increases with temperature. When added in the right proportion, their temperature drifts cancel, yielding a Zero Temperature Coefficient (ZTC) voltage. ⚙️ Two Major Architectures Voltage Mode BGR – Combines CTAT and PTAT voltages directly. It’s conceptually simple and widely used but faces limitations when operating at very low supply voltages. Current Mode BGR (Banba Architecture) – Combines CTAT and PTAT currents instead of voltages, enabling operation even below 1 V. It’s ideal for modern low-power systems, though it introduces additional design complexity and startup challenges. 📊 Voltage vs. Current Mode — In Essence The Voltage Mode BGR offers moderate power consumption and simpler startup but struggles with low-voltage headroom due to the amplifier’s limitations. The Current Mode BGR, on the other hand, excels in low-voltage and low-power operation, making it suitable for sub-1 V systems, but demands precise current mirror matching and careful startup design to avoid zero-current states. 💡 Why It Matters The BandGap Reference is a perfect blend of physics and circuit design — using the intrinsic properties of silicon to defy temperature variation. It’s not just a circuit; it’s a concept that bridges device physics with system reliability. 🧠 This presentation is part of my continuing journey in Analog IC Design, exploring how fundamental blocks evolve to meet the demands of low-power and high-precision applications. #AnalogDesign #BandGapReference #Cadence #CircuitDesign #VLSI #IIITB

We're taught that ground is a stable 0V reference. At high frequencies, this is false. Every physical element for instance, a via, a BGA ball, a package lead frame, has a small but critical amount of inductance (L). And, when multiple IC outputs switch simultaneously, they create a massive, near-instantaneous change in current, which is also known as (di/dt). This current rushing through the ground path's inductance induces a voltage spike, defined by the classic formula, V =L . di/dt Let's put numbers to it, > A single ground pin on a QFN package might have 2 nH of inductance. > If eight outputs switch at once, each driving 20 mA into a load with a 1 ns rise time, the total di/dt is roughly 160 A/µs. Plugging this into the formula, V=(2×10^−9H)×(160×10^6A/s) = 320mV Hence, now our IC's internal "ground" is no longer at 0V, and it has "bounced" up to 320 mV above the PCB's ground plane. #ElectronicsEngineering #HardwareDesign #PCBDesign #GroundBounce #HighSpeedDesign #SignalIntegrity #PowerIntegrity #EMC #EMI