Stars
Verilog design examples for use with the Signaloid C0-microSD
A simple, scalable, source-synchronous, all-digital DDR link
magic-trace collects and displays high-resolution traces of what a process is doing
riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way
Open Source Inventory Management System
A simple interface to GPIO devices with Raspberry Pi
Open source Altium Database Library with over 200,000 high quality components and full 3d models.
Generation of diagrams like flowcharts or sequence diagrams from text in a similar manner as markdown
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
An energy-efficient RISC-V floating-point compute cluster.
Rich is a Python library for rich text and beautiful formatting in the terminal.
A graphical processor simulator and assembly editor for the RISC-V ISA
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
A set of C and Python based utilities for the Signaloid C0-microSD
🚀 A Jekyll plugin to provide powerful supports for table, mathjax, plantuml, mermaid, emoji, video, audio, youtube, vimeo, dailymotion, soundcloud, spotify, etc.
A GitHub Pages-compatible, no-JavaScript fancy tables-generator using extended Markdown syntax.
USB DFU bootloader gateware / firmware for FPGAs
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
Two-Level Segregated Fit memory allocator implementation.